The present invention relates to a method of manufacturing a semiconductor device with an NAND structure such as an FET or a non-volatile memory, etc.
As an FET or a non-volatile memory with an NAND structure, the FET, etc., providing a number of CGs and SGs between an Si substrate 1 and a thin film of BL, etc., as shown in FIG. 1 and connected to the circuits as shown in FIG. 2 has been used. Such NAND type structured EEPROM, for example, as shown in FIG. 4C, has been produced by using a resistmask having mask lines 6 using the conventional photolithography shown in FIG. 4A and etching between the mask lines to produce spaced charge storage gate lines on an insulating layer 2 coated on the substrate 1, as shown in FIG. 4B. As a result, as shown in FIGS. 4B and 4C, each of the gate lines includes a portion of a charge storage gate layer 3, an insulating layer 4 and a control gate electrode layer 5 shown in FIG. 4A and, as shown in FIG. 4C, source and drain regions are formed in the substrate 1 by impurities implanted between the spaced gate lines.
In the resist process using the conventional photolithography, the transfer of the pattern with the NAND gate structure of line and space is carried out by a condition "line width=space length=minimum rule". When the minimum rule is lessened so as to produce finer lines in a conventional process, resistance of the gate line formed with the minimum width is gradually increased. Thus, as the countermeasure, forming a gate line material with a thick film is effectively carried out. Nevertheless, a large step is produced and the distance between a bit line which is wired on a gate line and a substrate impurity layer becomes large. Therefore, in order to obtain a suitable aspect ratio for a contact, to enlarge the contact in a horizontal direction is needed. Such enlargement of the contact is against the miniaturization. Further, to decrease resistance by increasing the impurity concentration disadvantageously becomes a cause of excess disappearance of data.